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FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Synthesis and Optimization of Digital Circuits
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An Emulator for Exploring RaPiD Configurable Computing Architectures
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
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FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
SLAAC: A Distributed Architecture for Adaptive Computing
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed for real time, in-field image processing applications. IPACE-V1 has ample memory and the capability of full or partial reconfiguration without the need of a host computer. This paper describes the architecture of the hardware board along with the software design environment. We shall also discuss a real-time background elimination application for video images implemented on iPACE-V1.