IEEE Transactions on Parallel and Distributed Systems
Design considerations for battery-powered electronics
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
An analytical high-level battery model for use in energy management of portable electronic systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Energy management for battery-powered embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
An opportunistic reconfiguration strategy for environmentally powered devices
Proceedings of the 3rd conference on Computing frontiers
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This paper presents a battery-efficient task execution methodology on Reconfigurable Computing (RC) Platforms which have multiple processing units. These processing units can be on-chip in the form of soft-processors, embedded processors or "Reconfigurable Tiles" where the reconfigurable area of an Field Programmable Gate Array (FPGA) is divided into fixed reconfigurable slots. Processing units can also be off-chip in the form of individual FPGAs and voltage-scalable processors. An application is modeled in the form of a precedence task graph. We assume that for each task in the task graph several different design-points are available which correspond to different voltage-frequency combinations for processors and different hardware implementations for FPGAs and "Reconfigurable Tiles". It is assumed that performance and total power consumption estimates for each design-point are available for any given implementation, including the peripheral components such as memory and display power usage. First we present an iterative heuristic algorithm for a single processing unit, which finds a sequence of tasks along with an appropriate design-point for each task, such that a deadline is met and the amount of battery energy used is as small as possible. Next, we extend this algorithm to multiple processing units in an RC platform. We used several real-world benchmarks to test the effectiveness of this methodology. Each benchmark was executed on one, two, three and four processing units and its power utilization was characterized by implementing it on a portable RC Platform called iPACE-V1. We present the results which show that choosing an appropriate execution mode is crucial for battery-efficient execution. We also show that parallel execution on multiple-processing units can actually be more battery-efficient than sequential execution on a single processing unit under certain circumstances.