GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A SAT Solver Using Reconfigurable Hardware and Virtual Logic
Journal of Automated Reasoning
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
On Implementing a Configware/Software SAT Solver
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment
HICSS '99 Proceedings of the Thirty-Second Annual Hawaii International Conference on System Sciences-Volume 3 - Volume 3
Solving Satisfiability in Combinational Circuits
IEEE Design & Test
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA based accelerator for 3-SAT conflict analysis in SAT solvers
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
FPGA-based hardware acceleration for Boolean satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A hardware relaxation paradigm for solving NP-hard problems
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
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Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator, where each clause is modeled as a shift register that is either right shifted, left shifted, or standstill according to whether the current assigned variable value satisfy, unsatisfy, or does not effect the clause, respectively. For a given problem instance, the effect of the value of each of its variables on its SAT formula is loaded in the FPGA on-chip memory. This results in less configuration effort and fewer hardware resources than other available SAT solvers. Also, we present a new approach for implementing conflict analysis based on a conflicting variables accumulator and priority encoder to determine backtrack level. Using these two new ideas, we implement an FPGA based SAT solver performing depth-first search with non-chronological conflict directed backtracking. We compare our SAT solver with other solvers through instances from DIMACS benchmarks suite.