GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Solving satisfiability problems using reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Acceleration of Satisfiability Algorithms by Reconfigurable Hardware
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment
HICSS '99 Proceedings of the Thirty-Second Annual Hawaii International Conference on System Sciences-Volume 3 - Volume 3
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver
Proceedings of the conference on Design, automation and test in Europe
Relieving capacity limits on FPGA-based SAT-solvers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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We present an FPGA-based hardware solution to the Boolean satisfiability (SAT) problem, with the main goals of scalability and speedup. In our approach the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. The experimental results and their analysis, along with the performance models are discussed. We show that an order of magnitude improvement in runtime can be obtained over MiniSAT (the best-in-class software based approach) by using a Virtex-4 (XC4VFX140) FPGA device. The resulting system can handle instances with as many as 10K variables and 280K clauses.