Retargetable instruction scheduling for pipelined processors
Retargetable instruction scheduling for pipelined processors
Detecting pipeline structural hazards quickly
POPL '94 Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Formal specification and simulation of instruction-level parallelism
EURO-DAC '94 Proceedings of the conference on European design automation
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL
Proceedings of the 7th International Workshop on Higher Order Logic Theorem Proving and Its Applications
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Simplifying the design and automating the verification of pipelines with structural hazards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Policies of System Level Pipeline Modeling
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic pipelining from transactional datapath specifications
Proceedings of the Conference on Design, Automation and Test in Europe
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We describe a SystemC library for specifying, modeling, and simulating hardware pipelines. The library includes a set of overloaded operators defining a pipeline expression language that allows the user to quickly specify the architecture of the pipeline. The pipeline expression is used to derive the connectivity of the SystemC modules that define the stages of the pipeline and to automatically insert latches and control modules between the stages to handle the proper routing of transactions through pipeline. Using the SystemC simulator the pipeline can then be simulated and evaluated. The pipeline expression language sits on top of SystemC, exposes all of the features of C++ and SystemC enabling the user to specify, evaluate, and analyze pipeline architectures.