Decision procedures and expressiveness in the temporal logic of branching time
Journal of Computer and System Sciences
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Verification of the Futurebus+ cache coherence protocol
Formal Methods in System Design - Special issue on symbolic model checking
Formal Methods in System Design - Special issue on symmetry in automatic verification
Symbolic Model Checking
NuSMV 2: An OpenSource Tool for Symbolic Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
On Model Checking for Non-Deterministic Infinite-State Systems
LICS '98 Proceedings of the 13th Annual IEEE Symposium on Logic in Computer Science
Proceedings of the 36th SIGCSE technical symposium on Computer science education
Efficient Symmetry Breaking for Boolean Satisfiability
IEEE Transactions on Computers
SANE: a protection architecture for enterprise networks
USENIX-SS'06 Proceedings of the 15th conference on USENIX Security Symposium - Volume 15
Ethane: taking control of the enterprise
Proceedings of the 2007 conference on Applications, technologies, architectures, and protocols for computer communications
OpenFlow: enabling innovation in campus networks
ACM SIGCOMM Computer Communication Review
NOX: towards an operating system for networks
ACM SIGCOMM Computer Communication Review
Shadow configuration as a network management primitive
Proceedings of the ACM SIGCOMM 2008 conference on Data communication
Practical declarative network management
Proceedings of the 1st ACM workshop on Research on enterprise networking
Communications of the ACM - Scratch Programming for All
Rethinking enterprise network control
IEEE/ACM Transactions on Networking (TON)
Software verification with BLAST
SPIN'03 Proceedings of the 10th international conference on Model checking software
Finding and reproducing Heisenbugs in concurrent programs
OSDI'08 Proceedings of the 8th USENIX conference on Operating systems design and implementation
FlowChecker: configuration analysis and verification of federated openflow infrastructures
Proceedings of the 3rd ACM workshop on Assurable and usable security configuration
Frenetic: a high-level language for OpenFlow networks
Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow
Virtualizing the network forwarding plane
Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow
Can the production network be the testbed?
OSDI'10 Proceedings of the 9th USENIX conference on Operating systems design and implementation
Nettle: taking the sting out of programming network routers
PADL'11 Proceedings of the 13th international conference on Practical aspects of declarative languages
Debugging the data plane with anteater
Proceedings of the ACM SIGCOMM 2011 conference
Header space analysis: static checking for networks
NSDI'12 Proceedings of the 9th USENIX conference on Networked Systems Design and Implementation
On the verification of sequential machines at differing levels of abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A safe, efficient update protocol for openflow networks
Proceedings of the first workshop on Hot topics in software defined networks
Abstractions for network update
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
A correct, zero-overhead protocol for network updates
Proceedings of the second ACM SIGCOMM workshop on Hot topics in software defined networking
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Formal verification has seen much success in several domains of hardware and software design. For example, in hardware verification there has been much work in the verification of microprocessors (e.g. [1]) and memory systems (e.g. [2]). Similarly, software verification has seen success in device-drivers (e.g. [3]) and concurrent software (e.g. [4]). The area of network verification, which consists of both hardware and software components, has received relatively less attention. Traditionally, the focus in this domain has been on performance and security, with less emphasis on functional correctness. However, increasing complexity is resulting in increasing functional failures and thus prompting interest in verification of key correctness properties. This paper reviews the formal verification techniques that have been used here thus far, with the goal of understanding the characteristics of the problem domain that are helpful for each of the techniques, as well as those that pose specific challenges. Finally, it highlights some interesting research challenges that need to be addressed in this important emerging domain.