Verified Optimizations for the Intel IA-64 Architecture

Authors:
Jim Grundy
Affiliations:
-
Venue:
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Year:
2000

Citing 3
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Abstract

This paper outlines a formal model of the Intel IA-64 architecture, and explains how this model can be used to verify the correctness of assembly-level code optimizations. The formalization and proofs were carried out using the HOL Light theorem prover.