Exploiting PSL standard assertions in a theorem-proving-based verification environment

Authors:
Youngsik Kim;Parija Sule;Nazanin Mansouri
Affiliations:
Syracuse University, Syracuse, New York;Syracuse University, Syracuse, New York;Syracuse University, Syracuse, New York
Venue:
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Year:
2005

Citing 3
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Assertion-Based Design

Assertion-Based Design

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Abstract

Assertion-based design is becoming more widely used in industry. However, little has been done to take advantage of existing design assertions in the theorem-proving verification environments. In this paper, we present our work on development of the semi-automated theorem-proving based verification system ROVERIFIC that makes use of existing design assertions. We have defined generic predicate templates that capture the semantics of PSL, and a subset of Verilog. ROVERIFIC uses these templates, and automatically compiles a design under verification (Verilog) and its assertions (PSL) into the higher-order predicates of the PVS [11] theorem proving system. Design verification can be subsequently conducted by proving the correctness properties.