Chip-level modeling with VHDL
A framework for behavioral synthesis from partial design structures
A framework for behavioral synthesis from partial design structures
A graphical hardware design language
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MILO: a microarchitecture and logic optimizer
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis techniques for digital systems design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An intermediate representation for behavioral synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Timing distribution in VHDL behavioral models
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
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This paper describes features of EXEL, a graphic language that gives the designer control over the behavioral synthesis process. Control is achieved by allowing the designer to partially specify the structural design into which the description is going to be compiled, or by binding desired variables and operators to particular components or connections, and binding desired operations to particular states of the final design. EXEL's compiler runs on SUN-3 workstations and is written in C and SUNVIEW.