Generating VHDL models from natural language descriptions

  • Authors:
  • Walling R. Cyre;Jim Armstrong;M. Manek-Honcharik;Alexander J. Honcharik

  • Affiliations:
  • The Bradley Department of Electrical Engineering, Virginia Tech, Blacksburg, Virginia;The Bradley Department of Electrical Engineering, Virginia Tech, Blacksburg, Virginia;The Bradley Department of Electrical Engineering, Virginia Tech, Blacksburg, Virginia;The Bradley Department of Electrical Engineering, Virginia Tech, Blacksburg, Virginia

  • Venue:
  • EURO-DAC '94 Proceedings of the conference on European design automation
  • Year:
  • 1994

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Abstract