High-Level Embedded System Specifications Based on Process Activation Conditions

Authors:
Wolfgang Boßung;Sorin Alexander Huss;Stephan Klaus
Affiliations:
Integrated Circuits and Systems Laboratory, Department of Computer Science, Darmstadt University of Technology, Germany;Integrated Circuits and Systems Laboratory, Department of Computer Science, Darmstadt University of Technology, Germany;Integrated Circuits and Systems Laboratory, Department of Computer Science, Darmstadt University of Technology, Germany
Venue:
Journal of VLSI Signal Processing Systems - Special issue on system level design
Year:
1999

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Abstract

High-level specifications for the behaviour of informationprocessing systems consist of data and control flow descriptions aswell as of timing requirements, which are to be met by feasibleimplementations. In contrast to systems specified as task graphs thisapproach is based on a functional partitioning. A process netdescription with conditional process activation is proposed.Furthermore, the simulation of token flow leads to a schedule thatsupports investigations of the timing analysis for the proposedCodesign Model (CDM). Predictions of the delay between any twoprocesses of the system are also possible, as well as the processingspeed of primary inputs and outputs, iteration times of determinedperiods, and hence, all derivable time criteria. A formal notationof process nets as cyclic graphs is given, which is shown to beuseful for the description of complex digital embedded systems. Theproperties of the processes involved are detailed. In general,scheduling with resource allocation on a graph structure, asdiscussed in this paper, is NP-complete. However, the advocated simulation method delivers detailedinformation on conditional paths of data and control flow in a CDM.The simulation can be interrupted at any point in time for anevaluation of corresponding results and for a subsequent refinementof the CDM. The outlined approach is intended for a capture and anaccessment of specifications in the conceptual phase of systemdevelopment. Resulting advantages and some restrictions aredemonstrated by means of an image processing system.