FunState—an internal design representation for codesign

Authors:
L. Thiele;K. Strehl;D. Ziegenbein;R. Ernst;J. Teich
Affiliations:
Computer Engineering and Networks Lab (TIK), Swiss Federal Institute of Technology (ETH), Zurich, Switzerland;Computer Engineering and Networks Lab (TIK), Swiss Federal Institute of Technology (ETH), Zurich, Switzerland;Institute of Computer Engineering (IDA), Technical University of Braunschweig, Braunschweig, Germany;Institute of Computer Engineering (IDA), Technical University of Braunschweig, Braunschweig, Germany;Computer Engineering Lab (DATE), University of Paderborn, Paderborn, Germany
Venue:
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Year:
1999

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Abstract

In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines.It is shown here how properties relevant for scheduling and verification of specification models like boolcan dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets may be represented in the FunState model. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in form of a periodic graph.