Verification of Real-Time Systems using Linear Relation Analysis
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
FunState—an internal design representation for codesign
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Automatic discovery of linear restraints among variables of a program
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Proceedings of the 4th ACM international conference on Embedded software
System-scenario-based design of dynamic embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical finite state machines with multiple concurrency models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static run-time mode extraction by state partitioning in synchronous process networks
Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems
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For modeling modern streaming-oriented applications, Process Networks (PNs) are used to describe systems with changing behavior, which must be mapped on a concurrent architecture to meet the performance and energy constraints of embedded devices. Finding an optimal mapping of Process Networks to the constrained architecture presumes that the behavior of the Process Network is statically known. In this paper we present a static analysis for synchronous PNs that extracts different run-time modes by using polyhedral abstraction. The result is a Mealy machine whose states describe different run-time modes and the edges among them represent transitions. This machine can be used to guide optimizing backend mappings from PNs to concurrent architectures.