Diagramming techniques for analysts and programmers
Diagramming techniques for analysts and programmers
Action diagrams: clearly structured program design
Action diagrams: clearly structured program design
Chip-level modeling with VHDL
Graphical notations for program design
ACM SIGSOFT Software Engineering Notes
Increasing design quality and engineering productivity through design reuse
DAC '93 Proceedings of the 30th international Design Automation Conference
A reuse scenario for the VHDL-based hardware design flow
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Flowchart techniques for structured programming
ACM SIGPLAN Notices
Structure charts a structured alternative to flowcharts
ACM SIGPLAN Notices
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Designer's productivity has become the key-factor of the development of electronic systems. An increasing application of design data reuse is widely recognized as a promising technique to master future design complexities. Since the intellectual property of a design is more and more kept in software-like hardware description languages (HDL), successful reuse depends on the availability of suitable HDL reverse engineering tools. This paper introduces new concepts for an integrated HDL reverse engineering tool-set and presents an implemented evaluation prototype for VHDL designs. Starting from an arbitrary collection of HDL source code files, several graphical and textual views on the design description are automatically generated. The tool-set provides novel hypertext techniques, expressive graphical code representations, a user-defined level of abstraction, and interactive configuration mechanisms in order to facilitate the analysis, adoption and upgrade of existing HDL designs.