Chip-level modeling with VHDL
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
| Hi-index | 0.00 |
As technology has evolved, the gate level has remained viable for the specification of digital systems solutions. We describe the gsim system for gate-level logic modeling and simulation. It consists of• a hardware description language (hdl)• a set of logic network measurements and validity checks to assure that the correct circuit has been specified• mechanisms for the application of stimuli and the monitoring of responses from the logic network under test.• extensive libraries, demonstrations, and tutorial materials to make the system easier to learn and to use.The gsim system specifically supports structured, top-down design practices and the multiple instantiation of basic units with hierarchy and iteration.