Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
Formal verification in a component-based reuse methodology
Proceedings of the 15th international symposium on System Synthesis
Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Generic integration infrastructure for IP-based design processes and tools with a unified XML format
Integration, the VLSI Journal - Special issue: IP and design reuse
Automation of IP qualification and IP exchange
Integration, the VLSI Journal - Special issue: IP and design reuse
Formal co-verification for soc design with colored petri net
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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