Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
An efficient reuse system for digital circuit design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Object-oriented reuse methodology for VHDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Design methodology for IP providers
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Component selection and matching for IP-based design
Proceedings of the conference on Design, automation and test in Europe
A Qualification Platform for Design Reuse
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
E-Design Based on the Reuse Paradigm
Proceedings of the conference on Design, automation and test in Europe
An XML Format Based Integration Infrastructure for IP Based Design
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A knowledge representation format for virtual IP marketplaces
ICCBR'03 Proceedings of the 5th international conference on Case-based reasoning: Research and Development
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Current and future SOC designs will use IP cores as basic building blocks. These IP cores have to fulfill defined quality characteristics. Conformance to these characteristics has to be checked automatically, as the increase in complexity makes manual checks infeasible. This article introduces IP quality aspects and describes the IP qualification platform which is able to check quality characteristics of digital soft IP. In order to distribute qualified IP it is essential to introduce an IP exchange process. More than 80% time and resource savings are expected through automated IP delivery which is based on a general IP transfer format.