DAC '97 Proceedings of the 34th annual Design Automation Conference
Design methodology for IP providers
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Model checking
Verification of embedded systems using a petri net based representation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
A Qualification Platform for Design Reuse
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
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There is an important trend towards design processes based on the reuse of predesigned components. We propose a formal verification approach which smoothly integrates with a component based sys tem-level design methodology. Once a timed Petri Net model corre sponding to the interface logic has been produced the correctness of the system can be formally verified. The verification is based on the interface properties of the connected components and on abstract models of their functionality, without assuming any knowledge regarding their implementation. We have both developed the theo retical framework underlying the methodology and implemented an experimental environment using model checking techniques.