Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step

Authors:
Chia-Ling (Lynn) Chang;Charles H.-P. Wen;Jayanta Bhadra
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;Freescale Semiconductor Inc., Austin, TX
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 8
Cited 0

A Comparison of Defect Models for Fault Location with IDDQ Measurements

Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results

ITC '98 Proceedings of the 1998 IEEE International Test Conference
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Eliminating the Ouija® Board: Automatic Thresholds and Probabilistic IDDQ Diagnosis

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions

ITC '04 Proceedings of the International Test Conference on International Test Conference
Prediction of leakage power under process uncertainties

ACM Transactions on Design Automation of Electronic Systems (TODAES)
CδIDDQ: improving current-based testing and diagnosis through modified test pattern generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Along with the shrinking CMOS process and rapid design scaling, both Iddq values and their variation of chips increase. As a result, the defect leakages become less significant when compared to the full-chip currents, making them more in-distinguishable for traditional Iddq diagnosis. Therefore, in this paper, a new approach called σ-Iddq diagnosis is proposed for reinterpreting original data and diagnosing failing chips, intelligently. The overall flow consists of two key components, (1) σ-Iddq transformation and (2) defect-syndrome matching: σ-Iddq transformation first manifests defect leakages by excluding both the process-variation and design-scaling impacts. Later, defect-syndrome matching applies data mining with a pre-built library to identify types and locations of defects on the fly. Experimental results show that an average of 93.68% accuracy with a resolution of 1.75 defect suspects can be achieved on ISCAS'89 and IWLS'05 benchmark circuits using a 45nm technology, demonstrating the effectiveness of σ-Iddq diagnosis.