CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient spectral techniques for sequential ATPG
Proceedings of the conference on Design, automation and test in Europe
Effective safety property checking using simulation-based sequential ATPG
Proceedings of the 39th annual Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
LOCSTEP: a logic-simulation-based test generation procedure
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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A simple and highly efficient logic-simulation-based test generator uses a genetic algorithm to achieve both high fault coverage and short test generation times.