Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Satisfiability on reconfigurable hardware
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Solving Boolean Satisfiability with Dynamic Hardware Configurations
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Solving Satisfiability Problems on FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Partitioning Methods for Satisfiability Testing on Large Formulas
CADE-13 Proceedings of the 13th International Conference on Automated Deduction: Automated Deduction
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Reducing Compilation Time of Zhong's FPGA-Based SAT Solver
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asynchronous circuit synthesis with Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast SAT solver algorithm best suited to reconfigurable hardware
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Synthesis of FSMs on the basis of reusable hardware templates
ISTASC'06 Proceedings of the 6th WSEAS International Conference on Systems Theory & Scientific Computation
| Hi-index | 0.00 |
This paper introduces ELVIS, a custom PLD that solves Boolean satisfiability (SAT) problems and presents a significant improvement over previous approaches. SAT is a core computer science problem with important commercial applications, which include timing verification, automated layout, and logic minimization and test pattern generation.ELVIS is the first massively parallel SAT-solver to support efficient loading of formulas and on-line clause addition with no instance-specific placement or routing. Furthermore, ELVIS requires significantly less hardware capacity than previous approaches. The design is easily scaled; it requires hardware that grows linearly with formula size. As such, it is the first to guarantee polynomial space and time complexity of formula loading. This avoids the laborious (NP-hard) placement and routing of each formula that has plagued previous approaches.The new approach can efficiently support dynamic clause addition, formula partitioning, implication heuristics and an unbounded number of variables per clause. Large-scale implementation of these optimizations and modifying ELVIS to realize a multi-chip board design are the goals of future research.