Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
New parallelization and convergence results for NC: a negotiation-based FPGA router
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
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We present schemes to reduce the compilation time of configurable hardware that solves Boolean Satisfiability. The SAT solver presented by Zhong et al in FCCM98 has a large compilation time overhead mainly due to placement and routing of many FPGAs. We attack the problem on 3 fronts. First, we partitioning the SAT solver into instance-specific and instance non-specific components. Secondly, we transform SAT instances to canonical forms; and finally we present a board-level multiple-chip architecture to solve large SAT instances. All these efforts amount to a reduction in placement and routing time to configure the configurable hardware. We are able to reduce the compilation time to mere routing time of the implication circuits for each instance of the SAT problem, given the best scenario.