DAC '98 Proceedings of the 35th annual Design Automation Conference
Hierarchical finite-state machines and their use for digital control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic Synthesis for Control Automata
Logic Synthesis for Control Automata
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Run-Time Management of Dynamically Recongigurable Designs
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Field-Programmable Logic: Catalyst for New Computing Paradigms
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Exploiting FPGA-Based Architectures and Design Tools for Problems of Reconfigurable Computations
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
A Configurable Hardware/Software Approach to SAT Solving
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
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This paper suggests a reusable hardware template (HT) for finite state machines (FSM) and a method for the synthesis of FSMs based on such a template. The HT is a circuit with a predefined structure that has already been implemented in hardware (for example, in FPGA). By reprogramming its RAM-blocks we can implement a different functionality of the FSM. The proposed method permits the translation of a given FSM specification (that takes into account the parameters of a particular HT) into bitstreams for reloading the RAM-blocks. Run-time modifications are also permitted with the aid of dual-port memory. Note that the resulting FSM circuits are very fast and any state transition is performed within one clock cycle. The designed C++ program provides synthesis, verification and modeling of FSMs. The synthesized circuits were implemented and tested in Xilinx FPGAs. The synthesis methods considered permit various target requirements to be satisfied, such as minimizing the complexity of the circuit and the possibility for changes in the circuit functionality.