Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Synthesis of FSMs on the basis of reusable hardware templates
ISTASC'06 Proceedings of the 6th WSEAS International Conference on Systems Theory & Scientific Computation
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This paper addresses the design and implementation of a configurable "combinatorial processor", a computational device, which can be used for solving different combinatorial problems. These can be characterized by a set of variables having a limited number of values with a corresponding set of operations that might be applied to these variables. Different mathematical models can be used to describe such tasks. We adopted a matrix representation, which is easier to treat in digital devices. The operations on discrete matrices are unique and cannot be efficiently performed on a general-purpose processor. Although the number of such operations grows exponentially with the number of variables, to solve a particular combinatorial problem a very small number of such operations is usually required. Hence the importance of providing for the dynamic change of operations. The paper presents an approach allowing the run-time modification of combinatorial computations via reloading the RAM-based configurable logic blocks of the FPGAs.