Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Minimal Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On static test compaction and test pattern ordering for scan designs
Proceedings of the IEEE International Test Conference 2001
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Improving Test Pattern Compactness in SAT-based ATPG
ATS '07 Proceedings of the 16th Asian Test Symposium
Dynamic Compaction for High Quality Delay Test
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Conflict-driven answer set solving
IJCAI'07 Proceedings of the 20th international joint conference on Artifical intelligence
Dynamic Compaction in SAT-Based ATPG
ATS '09 Proceedings of the 2009 Asian Test Symposium
A scalable method for the generation of small test sets
Proceedings of the Conference on Design, Automation and Test in Europe
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
Efficient SAT-Based Search for Longest Sensitisable Paths
ATS '11 Proceedings of the 2011 Asian Test Symposium
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SOCRATES: a highly efficient automatic test pattern generation system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Acceleration of SAT-Based ATPG for Industrial Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
COMPACTEST: a method to generate compact test sets for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Small-delay-fault ATPG with waveform accuracy
Proceedings of the International Conference on Computer-Aided Design
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
ATS '12 Proceedings of the 2012 IEEE 21st Asian Test Symposium
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT) is a robust alternative to classical structural ATPG. Due to the powerful reasoning engines of modern SAT solvers, SAT-based algorithms typically provide a high test coverage because of the ability to reliably classify hard-to-detect faults. However, a drawback of SAT-based ATPG is the test compaction ability. In this paper, we propose an enhanced dynamic test compaction approach which leverages the high implicative power of modern SAT solvers. Fault detection constraints are encoded into the SAT instance and a formal optimization procedure is applied to increase the detection ability of the generated tests. Experiments show that the proposed approach is able to achieve high compaction -- for certain benchmarks even smaller test sets than the currently best known results are obtained.