A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On identifying don't care inputs of test patterns for combinational circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On static test compaction and test pattern ordering for scan designs
Proceedings of the IEEE International Test Conference 2001
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
Dynamic Compaction for High Quality Delay Test
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved SAT-based ATPG: more constraints, better compaction
Proceedings of the International Conference on Computer-Aided Design
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This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern sets for ISCAS circuits. For industrial circuits it achieves much smaller test pattern sets than other methods in designs sensitive to decision order used in ATPG.