Minimizing FPGA Interconnect Delays
IEEE Design & Test
Segmented channel routability via satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TORCH: a design tool for routing channel segmentation in FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Hi-index | 0.00 |