Area-speed tradeoffs for hierarchical field-programmable gate arrays
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Wire length distribution for placements of computer logic
IBM Journal of Research and Development
Routing for symmetric FPGAs and FPICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Interconnect estimation for mesh-based reconfigurable computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
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Field Programmable Gate Arrays (FPGAs) haveemerged as the key technology for rapidly implementingdigital circuits in VLSI. Much research has been done ontheir architecture and applications. One particularlyimportant area of study is their routing implementation,which is greatly affected by the routing architecture androuting resources. This paper explores the effectiveutilization of a routing hierarchy that is present in thecurrently available commercial FPGAs. A stochasticmodel is adopted to investigate the routability onsymmetrical FPGAs containing a routing resourcehierarchy. The performance of our model is compared tothat of an FPGA without a routing hierarchy.Experimental methods are used to determine the switchconsumption of various routing resources. Results showthat integrating a routing resource hierarchy into FPGAscauses a design to consume fewer routing resources.Consequently, the speed of designs implemented in suchFPGAs can be greatly improved.