Quantitative Analysis of FPGA-based Database Searching

Authors:
N. Shirazi;D. Benyamin;W. Luk;P. Y. K. Cheung;S. Guo
Affiliations:
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124-3400, USA;Department of Electrical Engineering, UCLA, 56-125B, Engr. IV Bldg., Los Angeles, CA 90095, USA;Department of Computing, Imperial College, 180 Queen's Gate, London SW7 2BZ, UK;Department of Electrical Engineering, Imperial College, Exhibition Road, London SW7 2BT, UK;Philips Semiconductors, 811 E. Arques Ave. MS31, Sunnyvale, CA 94088-3409, USA
Venue:
Journal of VLSI Signal Processing Systems
Year:
2001

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Abstract

This paper reports two contributions to the theory and practice of using reconfigurable hardware to implement search engines based on hashing techniques. The first contribution concerns technology-independent optimisations involving run-time reconfiguration of the hash functions; a quantitative framework is developed for estimating design trade-offs, such as the amount of temporary storage versus reconfiguration time. The second contribution concerns methods for optimising implementations in Xilinx FPGA technology, which achieve different trade-offs in cell utilisation, reconfiguration time and critical path delay; quantitative analysis of these trade-offs are provided.