Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
A partitioning algorithm for system-level synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Performance of a software MPEG video decoder
MULTIMEDIA '93 Proceedings of the first ACM international conference on Multimedia
Tcl and the Tk toolkit
Experience with image compression chip design using unified system construction tools
DAC '94 Proceedings of the 31st annual Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
High-Level VLSI Synthesis
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Design of an Embedded Video Compression System - A Quantitative Approach
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Transport-Triggering versus Operation-Triggering
CC '94 Proceedings of the 5th International Conference on Compiler Construction
HW/SW Co-Design with PRAMs Using CoDES
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Linking System Design Tools and Hardware Design Tools
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
WWW based structuring of codesigns
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
DAC '96 Proceedings of the 33rd annual Design Automation Conference
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hardware/software co-design of an ATM network interface card: a case study
Proceedings of the 6th international workshop on Hardware/software codesign
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Speed-up estimation for HW/SW-systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
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The implementation of a cosynthesis design flow in the CASTLE system is presented. The design flow generates a synthesizable hardware description and a C, C++, or Fortran compiler for an application-oriented processor. The approach is illustrated by the design of an embedded video compression system which can be integrated into the video card of a PC. The design flow is structured as follows: First, the requirements of the application programs are analyzed. Based on these analysis results, the designer decides on the appropriate processor structure. The processor structure is entered on a block diagram level into the CASTLE system by using a schematic entry. The CASTLE system performs the processor cosynthesis based on a VHDL library of processor components. Several processor datapaths for the video compression system were synthesized to illustrate the trade-offs between flexibility and performance when designing application-oriented processors.