Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
A hardware environment for prototyping and partitioning based on multiple FPGAs
EURO-DAC '94 Proceedings of the conference on European design automation
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
EURO-DAC '94 Proceedings of the conference on European design automation
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Constrained software generation for hardware-software systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Design flow for hardware/software cosynthesis of a video compression system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
An approach to the adaptation of estimated cost parameters in the COSYMA system
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Automatic structuring and optimization of hierarchical designs
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models
Proceedings of the 6th international workshop on Hardware/software codesign
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Computing communication cost by Petri nets for hardware/software codesign
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
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HW/SW-codesign has been applied to a wide range of applications. Several partitioning methods have been suggested. Thus the designer selects modules for HW or SW-implementation for the best possible performance within a set of performance and design constraints. This paper describes an estimation method to approximate a priori the entire system performance. The estimation method has been integrated into the codesign tool COD and first results could be generated. The estimated speed-up has been determined for a ciphering algorithm and has been compared to the speed-up of the entire HW/SW-system. The estimation speed-up matches the final speedup.