Area/delay estimation for digital signal processor cores

  • Authors:

  • Yuichiro Miyaoka;Yoshiharu Kataoka;Nozomu Togawa;Massao Yanagisawa;Tatsuo Ohtsuki

  • Affiliations:

  • Dept. of Electronics, Information and Communication Engineering, Waseda University;Matsushita Communication Industrial Co., Ltd and Dept. of Electronics, Information and Communication Engineering, Waseda University;Advanced Research Institute for Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan;Dept. of Electronics, Information and Communication Engineering, Waseda University;Dept. of Electronics, Information and Communication Engineering, Waseda University

  • Venue:
  • Proceedings of the 2001 Asia and South Pacific Design Automation Conference
  • Year:
  • 2001

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Abstract

Hardware/software partitioning is one of the key processes in a hardware/software cosynthesis system for digital signal processor cores. In hardware/software partitioning, area and delay estimation of a processor core plays an important role since the hardware/software partitioning process must determine which part of a processor core should be realized by hardware units and which part should be realized by a sequence of instructions based on execution time of an input application program and area of a synthesized processor core. This paper proposes area and delay estimation equations for digital signal processor cores. For area estimation, we show that total area for a processor core can be derived from the sum of area for a processor kernel and area for additional hardware units. Area for processor kernel can be mainly obtained by minimum area for processor kernel and overheads for adding hardware units and registers. Area for a hardware unit can be mainly obtained by its type and operation bit width. For delay estimation, we show that critical path delay for a processor core can be derived from the delay of a hardware unit which is on the critical path in the processor core. Experimental results demonstrate that errors of area estimation are less than 2% and errors of delay estimation are less than 2ns when comparing estimated area and delay with logic-synthesized area and delay.