Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Integrated Partitioning and Scheduling for Hardware/Software Co-design
ICCD '98 Proceedings of the International Conference on Computer Design
Instruction set and functional unit synthesis for SIMD processor cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that we can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.