Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Synthesis of instruction sets for pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
MetaCore: an application specific DSP development system
DAC '98 Proceedings of the 35th annual Design Automation Conference
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Integrated Partitioning and Scheduling for Hardware/Software Co-design
ICCD '98 Proceedings of the International Conference on Computer Design
A hardware/software partitioning algorithm for SIMD processor cores
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.