Instruction set and functional unit synthesis for SIMD processor cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A hardware/software partitioning algorithm for SIMD processor cores
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Hardware-software co-synthesis of hard real-time systems with reconfigurable FPGAs
Computers and Electrical Engineering
Hardware/software codesign for a fuzzy autonomous road-following system
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Hi-index | 0.01 |
Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results in all the task graphs in our experiments.