Automated fingerprint recognition using structural matching
Pattern Recognition
Memory estimation for high level synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
On-Line Fingerprint Verification
IEEE Transactions on Pattern Analysis and Machine Intelligence
Memory size estimation for multimedia applications
Proceedings of the 6th international workshop on Hardware/software codesign
Exact memory size estimation for array computations without loop unrolling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Security Engineering: A Guide to Building Dependable Distributed Systems
Security Engineering: A Guide to Building Dependable Distributed Systems
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
Proceedings of the 40th annual Design Automation Conference
Biometric Recognition: Security and Privacy Concerns
IEEE Security and Privacy
Interactive Cosimulation with Partial Evaluation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Efficient fingerprint-based user authentication for embedded systems
Proceedings of the 42nd annual Design Automation Conference
Fingerprint verification system involving smart card
ICISC'02 Proceedings of the 5th international conference on Information security and cryptology
FPGA-based Personal Authentication Using Fingerprints
Journal of Signal Processing Systems
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This paper describes a secure and memory-efficient embedded fingerprint verification system. It shows how a fingerprint verification module originally developed to run on a workstation can be transformed and optimized in a systematic way to run real-time on an embedded device with limited memory and computation power. A complete fingerprint recognition module is a complex application that requires in the order of 1000 M unoptimized floating-point instruction cycles. The goal is to run both the minutiae extraction and the matching engines on a small embedded processor, in our case a 50 MHz LEON-2 softcore. It does require optimization and acceleration techniques at each design step. In order to speed up the fingerprint signal processing phase, we propose acceleration techniques at the algorithm level, at the software level to reduce the execution cycle number, and at the hardware level to distribute the system work load. Thirdly, a memory trace map-based memory reduction strategy is used for lowering the system memory requirement. Lastly, at the hardware level, it requires the development of specialized coprocessors. As results of these optimizations, we achieve a 65% reduction on the execution time and a 67% reduction on the memory storage requirement for the minutiae extraction process, compared against the reference implementation. The complete operation, that is, fingerprint capture, feature extraction, and matching, can be done in real-time of less than 4 seconds.