Parallel thinning with two-subiteration algorithms
Communications of the ACM
Thinning Methodologies-A Comprehensive Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Fingerprint Image Enhancement: Algorithm and Performance Evaluation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Fingerprint Matching Using an Orientation-Based Minutia Descriptor
IEEE Transactions on Pattern Analysis and Machine Intelligence
Fingerprint enhancement with dyadic scale-space
Pattern Recognition Letters
Efficient fingerprint-based user authentication for embedded systems
Proceedings of the 42nd annual Design Automation Conference
Microcoded coprocessor for embedded secure biometric authentication systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient and secure fingerprint verification for embedded devices
EURASIP Journal on Applied Signal Processing
A Self-Contained Biometric Sensor for Ubiquitous Authentication
IPC '07 Proceedings of the The 2007 International Conference on Intelligent Pervasive Computing
Handbook of Fingerprint Recognition
Handbook of Fingerprint Recognition
An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Benchmarking quality-dependent and cost-sensitive score-level multimodal biometric fusion algorithms
IEEE Transactions on Information Forensics and Security - Special issue on electronic voting
Computer
A hybrid biometric cryptosystem for securing fingerprint minutiae templates
Pattern Recognition Letters
A Multicore Embedded Processor for Fingerprint Recognition
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Fingerprint image processing acceleration through run-time reconfigurable hardware
IEEE Transactions on Circuits and Systems II: Express Briefs
Fake fingerprint detection by odor analysis
ICB'06 Proceedings of the 2006 international conference on Advances in Biometrics
A fingerprint authentication system based on mobile phone
AVBPA'05 Proceedings of the 5th international conference on Audio- and Video-Based Biometric Person Authentication
An ultra-low memory fingerprint matching algorithm and its implementation on a 32-bit smart card
IEEE Transactions on Consumer Electronics
Flexible VLIW processor based on FPGA for efficient embedded real-time image processing
Journal of Real-Time Image Processing
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The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.