Fingerprint image processing acceleration through run-time reconfigurable hardware

  • Authors:

  • M. Fons;F. Fons;E. Cantó

  • Affiliations:

  • Development of Embedded Systems Research Group, Department of Electronic, Electrical and Automatic Control Engineering, Universitat Rovira i Virgili, Tarragona, Spain;Development of Embedded Systems Research Group, Department of Electronic, Electrical and Automatic Control Engineering, Universitat Rovira i Virgili, Tarragona, Spain;Development of Embedded Systems Research Group, Department of Electronic, Electrical and Automatic Control Engineering, Universitat Rovira i Virgili, Tarragona, Spain

  • Venue:
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • Year:
  • 2010

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Abstract

To the best of the authors' knowledge, this is the first brief that implements a complete automatic fingerprint-based authentication system (AFAS) application under a dynamically partial self-reconfigurable field-programmable gate array (FPGA). The main benefits of this implementation are the acceleration of the processing reached by the parallelism inherent to the hardware design, the high level of integration, the consequent security and reliability improvements provided by the usage of a system-on-programmable-chip device that is able to embed the main components of the application in a single chip, and the low cost achieved by the whole system due to the reconfigurability performance featured by the suggested FPGA. All these factors result in an outstanding system that is able to authenticate the identity of any user by means of those distinctive characteristics available in fingerprints. This brief reveals the advantages of run-time reconfigurable hardware in the implementation of those embedded systems demanding real-time performance at low cost. The minimization of the reconfiguration overhead by means of the proper sizing of the reconfigurable region in the FPGA and the design of a hardware configuration controller that is able to reach the maximum configuration rates allowed by the technology (3.2 Gb/s) are key factors to succeed in the development of the embedded AFAS application. The proposed system, which is implemented by means of hardware-software co-design techniques under a Virtex4 XC4VLX25 FPGA working at 100 MHz, is able to overcome in one order of magnitude the execution time performance achieved by a personal computer platform based on an Intel Core2Duo microprocessor running at 1.83 GHz.