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IEEE Transactions on Computers
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IEEE Transactions on Parallel and Distributed Systems
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This paper presents an automatic method to generate a Parallel PU (Processing Unit) for an algorithm with non-affine array references. The PU processes data according to a userdefined functionality and access data through an optimized memory access controller. The parallelism is achieved jointly through data and computation tiling. A generated TTC (Tile Transfer Controller) ensures the distribution of data tiles from external to local memories. For a given application and a user defined level of parallelism, a set of possible data partitioning is explored and the solutions with the minimal internal memory and the best temporal performances are chosen. In this work, the automatic method is used as a front-end of the High-Level Synthesis. For each chosen solution a whole synthesizable C-model including the TTC is generated.