High-bandwidth data memory systems for superscalar processors
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Reconfigurable caches and their application to media processing
Proceedings of the 27th annual international symposium on Computer architecture
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A Library of Memory Controllers for an Image Processing Prototyping System
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A quantitative analysis of the speedup factors of FPGAs over processors
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Computer Organization and Architecture: Designing for Performance (7th Edition)
Computer Organization and Architecture: Designing for Performance (7th Edition)
Automatic On-chip Memory Minimization for Data Reuse
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays
Microelectronics Journal
A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots
Journal of Signal Processing Systems
Run-time self-reconfigurable 2D convolver for adaptive image processing
Microelectronics Journal
Efficient memory architecture for image processing
International Journal of Circuit Theory and Applications
Design for Embedded Image Processing on FPGAs
Design for Embedded Image Processing on FPGAs
FPGA-based real-time optical-flow system
IEEE Transactions on Circuits and Systems for Video Technology
A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Hi-index | 0.00 |
In Field Programmable Gate Array (FPGA) efficient utilization of on-chip Static Random Access Memory (SRAM) is extremely important for most applications especially for image processing. True Dual Port (TDP) SRAM and Single Port (SP) SRAM are typically available SRAMs for image processing algorithms. But in case of data access policy changes, the memories need to be redesigned. Hence on-chip memory architecture capable of scanning the data in different ways without redesigning is required. In the proposed sub-bank Dual Port (DP) memory architecture, SP SRAM has been modified to function as a TDP SRAM, with high throughput and less power consumption. It also provides higher level of abstraction suitable for image processing algorithms with the help of two-port memory control unit, clock and address generators. The proposed sub-bank memory architecture and its system is implemented and verified for Lapped Biorthogonal Transform based Low complexity Zerotree Codec (LBT-LZC), an image coding algorithm. By considering the significant factors such as resource utilization, time and power, the proposed system outperforms TDP SRAMs.