FPGA based efficient on-chip memory for image processing algorithms
Microelectronics Journal
VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms
International Journal of Circuit Theory and Applications
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This Letter presents a novel purpose-designed architecture to realize efficient dual-port memory structures for image processing applications. The main innovation proposed here is the exploitation of single-port (SP) sub-banks to achieve the same data bandwidth offered by a true dual-port (TDP) memory, but significantly reducing the access time and resources requirement. When compared with a conventional TDP memory bank, the proposed strategy requires up to 25% less silicon area and consumes up to 9% lower power. It also exhibits an access time up to 15% lower. When used within an Actel FPGA RTAX device to realize an image compressor based on the 2D DWT and the SPIHT algorithm, the memory structure proposed here allows reaching an 11 Mpixels/s frame-rate, which is 77% higher than that achieved by simply instantiating the SP memory banks available on chip. Copyright © 2010 John Wiley & Sons, Ltd.