Affine-by-statement scheduling of uniform and affine loop nests over parametric domains

Automatic Mapping of System of N-Dimensional Affine Recurrence Equations (SARE) onto Distributed Memory Parallel Systems

IEEE Transactions on Software Engineering - Special issue on architecture-independent languages and software tools for parallel processing

Data and memory optimization techniques for embedded systems

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Loop parallelization algorithms

Compiler optimizations for scalable parallel systems

Communication-free partitioning of nested loops

Compiler optimizations for scalable parallel systems

Scheduling Functions for Spatiotemporal Mapping of d-Dimensional Algorithms with Homogeneous Dependences on (d-2)-Dimensional Parallel Architectures

Cybernetics and Systems Analysis

High Level Software Synthesis of Affine Iterative Algorithms onto Parallel Architectures

HPCN Europe 2000 Proceedings of the 8th International Conference on High-Performance Computing and Networking

A consistent generation of pipeline parallelism and distribution of operations and data among processors

Programming and Computing Software

Global memory optimisation for embedded systems allowed by code duplication

SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems

Incremental hierarchical memory size estimation for steering of loop transformations

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications

Journal of Signal Processing Systems

Trade-offs in loop transformations

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Systematic preprocessing of data dependent constructs for embedded systems

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Compositional approach applied to loop specialization

Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing