Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

Authors:
Nikolaos Kroupis;Nikolaos Zervas;Minas Dasygenis;Konstantinos Tatas;Antonios Argyriou;Dimitrios Soudris;Antonios Thanailakis
Affiliations:
Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece;ALMA Technologies, Attika, Greece GR 19009;Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece;Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece;School of Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta, USA;Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece;Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece
Venue:
Journal of VLSI Signal Processing Systems
Year:
2006

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Abstract

The continuous increase of the computational power of programmable processors has established them as an attractive design alternative, for implementation of the most computationally intensive applications, like video compression. To enforce this trend, designers implementing applications on programmable platforms have to be provided with reliable and in-depth data and instruction analysis that will allow for the early selection of the most appropriate application for a given set of specifications. To address this need, we introduce a new methodology for early and accurate estimation of the number of instructions required for the execution of an application, together with the number of data memory transfers on a programmable processor. The high-level estimation is achieved by a series of mathematical formulas; these describe not only the arithmetic operations of an application, but also its control and addressing operations, if it is executed on a programmable core. The comparative study, which is done using three popular processors (ARM, MIPS, and Pentium), shows the high efficiency and accuracy of the methodology proposed, in terms of the number of executed (micro-)instructions (i.e. performance) and the number of data memory transfers (i.e. memory power consumption). Using the proposed methodology we estimated an average deviation of 23% in our estimated figures compared with the measurements taken from the real execution on the CPUs.