A Memory Management Approach for Efficient Implementation of Multimedia Kernels on Programmable Architectures

Authors:
M. Dasigenis;N. Kroupis;A. Argyriou;K. Tatas;D. Soudris;A. Thanailakis;N. Zervas
Affiliations:
-;-;-;-;-;-;-
Venue:
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Year:
2001

Citing 0
Cited 2

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Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

Journal of VLSI Signal Processing Systems

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Abstract

Abstract: A methodology for power optimization of the data memory hierarchy and instruction memory, is introduced. The impact of the methodology on a set of widely used multimedia application kernels, namely Full Search (FS), Hierarchical Search (HS), Parallel Hierarchical One Dimension Search (PHODS), and Three Step Logarithmic Search (3SLS), is demonstrated. We find the power optimal data memory hierarchy applying the appropriate data-use transformation, while the instruction power optimization is done using suitable cache memory. Using data-reuse transformations, performance optimizations techniques, and instruction-level transformations, we perform exhaustive exploration of all the possible alternatives to reach power efficient solutions. Concerning the embedded processor ARM, the experimental results prove the efficiency of the methodology in terms of power for all the multimedia kernels.