A systematic approach to design low-power video codec cores
EURASIP Journal on Embedded Systems
Rapid-prototyping emulation system co-emulation modelling interface for systemC real-time emulation
ICS'08 Proceedings of the 12th WSEAS international conference on Systems
Combined simulation and emulation setup for complex image processing algorithms in VHDL
Proceedings of the 6th FPGAworld Conference
Hierarchical multi-agent protection system for NoC based MPSoCs
Proceedings of the International Workshop on Security and Dependability for Resource Constrained Embedded Systems
Enhancing network-on-chip components to support security of processing elements
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
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This paper presents a methodology for incorporating intellectualproperty (IP) cores that are implemented withSRAM-based FPGA logic into an existing hardware simulationenvironment for functional simulation and evaluationpurposes, using a simple serial communication interfacebased on the IEEE 1149.1 standard (also known asJTAG) with minimal hardware requirements. We also describea prototype software/hardware implementation of theproposed approach and present a case study to demonstratethe feasibility of our approach.