High speed JPEG coder based on modularized and pipelined architecture with distributed control

Authors:
Fahad Ali Mujahid;Eun-Gu Jung;Dong-Soo Har;Jun-Hee Hong;Hoi-Jeong Lim
Affiliations:
Department of Information and Communications, Gwangju Institute of Science and Technology, Republic of Korea;Department of Information and Communications, Gwangju Institute of Science and Technology, Republic of Korea;Department of Information and Communications, Gwangju Institute of Science and Technology, Republic of Korea;Department of Electrical Engineering, Kyungwon University;Department of Orthodontics School of Dentistry, Dental Science Research Institute Chonnam National University
Venue:
PCM'05 Proceedings of the 6th Pacific-Rim conference on Advances in Multimedia Information Processing - Volume Part I
Year:
2005

Citing 4
Cited 0

Design and implementation of JPEG encoder IP core

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Behavioral Synthesis and Component Reuse with VHDL

Behavioral Synthesis and Component Reuse with VHDL
A single chip motion JPEG codec LSI

IEEE Transactions on Consumer Electronics
A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

The design of an efficient reusable IP based Extended JPEG encoder is presented in this paper. This encoder uses user-defined quantization and Huffman tables that can be reconfigured at run-time. It has a modularized and pipelined architecture with distributed control for each block. A simple interface makes integration of the modules in various systems simple and straightforward. The design when targeted on FPGA operated at speed of up to 90MHz and when mapped on 0.25μm CMOS process the design can operate at speeds over 450MHz, which is faster than any of the similar JPEG encoder designs reported.