FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A JPEG Chip for Image Compression and Decompression
Journal of VLSI Signal Processing Systems
An SoC architecture and its design methodology using unifunctional heterogeneous processor array
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
High speed JPEG coder based on modularized and pipelined architecture with distributed control
PCM'05 Proceedings of the 6th Pacific-Rim conference on Advances in Multimedia Information Processing - Volume Part I
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We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels×480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products