Behavioral Synthesis and Component Reuse with VHDL
Behavioral Synthesis and Component Reuse with VHDL
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Hierarchical VHDL Libraries for DSP ASIC Design6
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
A single chip motion JPEG codec LSI
IEEE Transactions on Consumer Electronics
Development of low power MPEG1/JPEG encode/decode IC
IEEE Transactions on Consumer Electronics
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This paper describes the successful implementation of a hardware demonstrator for real-time JPEG standard colour image compression and decompression at picture refresh rates up to 25 frames per second using an FPGA-centric processing platform and design-reusable application-specific IP cores. The FPL device programming netlists for both JPEG encode and decode are directly derived from commercially available semiconductor Intellectual Property (IP Core) designs for Motion-JPEG applications; the target FPL devices form the core processing element in a commercial off-the-shelf reconfigurable module-based hardware platform for DSP and image processing applications. Performance metrics are presented for Xilinx Virtex and Altera APEX devices, and compared with semicustom ASIC implementations.