Computer arithmetic algorithms
Computer arithmetic algorithms
Journal of VLSI Signal Processing Systems - Special issue: video/image signal processing
Introduction to data compression (2nd ed.)
Introduction to data compression (2nd ed.)
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
A prototype VLSI chip architecture for JPEG image compression
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A single chip motion JPEG codec LSI
IEEE Transactions on Consumer Electronics
Development of low power MPEG1/JPEG encode/decode IC
IEEE Transactions on Consumer Electronics
FPGA based implementation of baseline JPEG decoder
Proceedings of the 7th International Conference on Frontiers of Information Technology
Low power hardware-based image compression solution for wireless camera sensor networks
Computer Standards & Interfaces
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JPEG is an international standard for still-image compression/decompression and has been widely implemented in hardware. In this paper, we describe the development of a JPEG chip which employs a single-chip implementation and an efficient architecture of Huffman codec. Firstly, we use VHDL (VHSIC Hardware Description Language) to describe the behavior of the chip. Each functional block of the chip is defined and simulated. An architecture consisting of two RAMs is adopted to reduce the size of the Huffman tables. Then we verify the functionality of our design with field programmable gate arrays (FPGAs) on circuit boards. Finally, a single chip is implemented using the standard cell design approach with the 0.6 μ triple-metal process. The chip is compliant with the JPEG baseline system and can work in real time at any compression ratio. The chip contains 411,745 transistors, with a chip size of 6.6 × 6.9 mm2.