Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
Energy-efficient acceleration of MPEG-4 compression tools
EURASIP Journal on Embedded Systems
UML based evaluation of reconfigurable shape adaptive DCT for embedded stream processing
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
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Shape-adaptive block-based texture coding schemes such as the shape-adaptive discrete cosine transform (SA-DCT) raise the need for an architecture which performs efficiently the transform of variable length N. For an implementation requiring standard DCT and SA-DCT, it is advantageous to have a VLSI architecture which can be configured to compute both schemes. Existing fast algorithms usually consider only the standard DCT of fixed-size length and lack regular structure leading to complex routing. This paper discusses two different architectures satisfying the given requirement in terms of scalability, modularity, and regularity. The first proposed architecture represents a time-recursive fully modular, but nonefficient, structure regarding the number of operation counts. The second proposed feedforward architecture overcomes problems of numerical instability found in time-recursive structure. Both architectures are modeled in VHDL and synthesized using an 0.7-μm two metal-layers CMOS technology for comparison. The design in VHDL is kept generic so that new SA-DCT cores can be easily generated to produce application tailored circuits